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Programs and Instructions

Ultimately, a program has to be represented as a sequence of instructions in memory. Each instruction specifies either one data manipulation step or a control action. Normally, instructions are executed in sequence. The machine is initialized with the program counter holding the memory location of the first instruction from the program and then the fetch-decode-execute cycle is started. The CPU sends a fetch request to memory specifying the location specified by the PC (program counter); it receives back the instruction and stores this in the Instruction Register (IR). The PC is then updated so that it holds the address of the next instruction in sequence. The instruction in the IR is then decoded and executed. Sometimes, execution of the instruction will change the contents of the PC. This can happen when one gets a "branch" instruction (these instructions allow a program to do things like skip over processing steps that aren't required for particular data, or go back to the start of some code that must be repeated many times).

A CPU is characterized by its instruction repertoire – the set of instructions that can be interpreted by the circuits in the timing and control unit and executed using the arithmetic logic unit. (Instructions are usually given short "mnemonic" names – names that have been chosen to remind one of the effect achieved by the instruction, like ADD and CLeaR.).

Different CPU architectures have different instruction sets. There will be lots of instructions that are common – ADD, SUB, etc. But each architecture will have its own special instructions that are not present on the other. Even when both architectures have similar instructions, e.g. the compare and conditional branch instructions, there may be differences in how these work. An instruction is represented by a set of bits. A few CPUs have fixed size instructions; on such machines, every instruction is 16-bits, or 32-bits or whatever. Most CPUs allow for different sizes of instructions. An instruction will be at least 16-bits in size, but may have an additional 16, 32, or more bits.

The first few bits of an instruction form the "Op-code" (operation code). These bits identify the data manipulation or control operation required. Again CPUs vary; some use a fixed size op-code, most have several different layouts for instructions with differing numbers of bits allocated for the op-code. If a CPU uses a fixed size op-code, decoding is simple. The timing and control component will implement a form of multiway switch. The meaning of the remaining bits of an instruction depends on the actual instruction. Many instructions require that data be specified. Thus, an ADD instruction needs to identify which two values are to be summed, and must also specify a place where the result should be stored. Often some of this information can be implicit. An ADD instruction can be arranged so that the sum of the two specified values always replaces the first value wherever this was stored.

Although some data locations can be implicit, it is necessary to define either the source or destination locations for the other data. Sometimes a program will need to add numbers that are already held in data registers in the CPU; at other times, the program may need to fetch additional data from memory. So sometimes the "operand description" part of an add instruction will need to identify the two CPU data registers that are to be used; other times, the "operand description" will have to identify one CPU register and one memory location. Occasionally, the "operand description" part might be used to identify a CPU register and the value that is to added to that register's existing contents. It is here that things get a bit complex. CPUs have many different ways of encoding information about the registers to be used, the addresses of memory locations, and the use of explicit data values. A particular machine architecture will have a set of "addressing modes" – each mode specifies a different way of using the bits of the operand description to encode details concerning the location of data values. Different architectures have quite different sets of addressing modes. Some instructions don't need any data. For example, the "Bcc" (conditional branch) group instructions use only information recorded in the CPU's Flags register. These instructions have different ways of using the operand bits of instruction word. Often, as with the Bcc instructions, the operand bits encode an address of an instruction that is to be used to replace the current contents of the program counter. Replacing the contents of the PC changes the next instruction executed.

Vocabulary Notes

ultimately ['AltimitlI]– в кінцевому рахунку, в кінці кінців

to execute – виконувати, реалізовувати

in sequence – послідовно

to skip over – перескакувати

to implement –виконувати, забезпечувати інструментами, постачати

architecture ['RkItektS(q)] – побудова, структура організації

to initialize [I'nISlaiz] – повертати в початковий стан

a fetch – виборка, виклик (команди чи даних з пам’яті)

to fetch – достати, приносити

request [ri'kwest] – прохання, вимога, запрос, заявка

instruction repertoire ['repqtwR] – система (набір) команд

to remind – нагадувати

to achieve [q'tSJv] – досягати, доводити до кінця, виконувати

to compare – порівнювати

a layout– розміщення, схема розміщення, формат

multiway switch – багатопозиційний перемикач, багатоканальний перемикач

implicit [Im'plIsIt] – не явно виражений, скритий

destination – призначення

contents– зміст, суть, значення

explicit [Iks'plIsIt] – явний, відкритий, прямий

to specify – точно визначати, встановлювати, детально викладати інформацію

Instruction Register – регістр команд

bit – мінімальна одиниця інформації, подвійний розряд


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